1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a sense amplifier for reading out data of a selected memory cell as a voltage to a bit line and converting the readout voltage into a current, and a current detection type read data bus amplifier (sense buffer: S/B) for flowing a current to amplify data.
2. Description of the Related Art
FIGS. 1A to 1C show the arrangement of a DRAM as a typical example of a semiconductor memory. As shown in FIG. 1A, a one-chip 256M (megabit)-DRAM 1 has four 64M-blocks 2 on the chip, and each 64M-block 2 is divided into four banks (Bank0 to Bank3). FIG. 1B shows the internal arrangement of one bank. One bank incorporates, in the column direction, sixteen blocks 4 each having eight memory cell arrays 3 in the row direction.
FIG. 1C shows the internal arrangement of one block 4. Sense amplifiers (a plurality of S/As 5) are arranged above and below each memory cell array 3 in the block 4 (for example, one S/As 5 comprises four sense amplifiers). As shown in FIG. 1B, secondary amplifiers (AMPs) 6 each made up of, e.g., four sense buffers (S/Bs) are arranged on the final row in the bank for respective columns.
Word lines and bit lines perpendicular to each other are laid out in the bank, and memory cells formed at their intersections constitute the memory cell array 3. For example, in a data read, when a set of word and bit lines is selected by an externally input address, data of the memory cell at the intersection between the selected word and bit lines is read out as a voltage having a very small amplitude to the bit line. This voltage is amplified by a sense amplifier 5a, further amplified by the secondary amplifier 6, and then externally output.
Note that the word line is selected based on a signal obtained by decoding an input address by a main word decoder (MW/Ds) and a sub-word decoder (SW/Ds). The column line is selected based on a signal obtained by decoding an input address by a column decoder (C/Ds). A sense amplifier 5 to be operated is selected based on a read enable signal rclex generated by a read controller (rclrgen) based on an address.
As shown in FIG. 1C, the sense amplifier 5a is a direct sense amplifier in which bit lines BL and /BL ("/" indicates an inverted signal) are connected to the gates of n-channel transistors. That is, the bit lines BL and /BL are respectively connected to the gates of two n-channel transistors 7. The sources or drains of the transistors 7 are respectively connected to read data buses RLDBX and RLDBZ via n-channel transistors 8 for selecting a column line CL. The drains or sources of the n-channel transistors 7 receive the read enable signal rclex.
In a standby state (precharge state), the read enable signal rclex is at "H", the n-channel transistors 7 are OFF, so no read detection current flows through the read data buses RLDBX and RLDBZ. When the read enable signal rclex changes to "L", a large current flows through the high-potential side of the n-channel transistors 7 in accordance with the voltage difference between a pair of bit lines BL and /BL selected by a column address. An amplifier 11 detects and amplifies a current difference corresponding to the amplitude of the pair of bit lines BL and /BL, so as to flow a read detection current through the read data buses RLDBX and RLDBZ.
In a data write, n-channel transistors 9 for selecting the column line CL are turned on, n-channel transistors 10 for selecting a write column line WCL are turned on, and data input from write data buses WLDBX and WLDBZ are transmitted to the pair of bit lines BL and /BL. The data is written in the memory cell at the intersection between the pair of bit lines BL and /BL and a word line (not shown).
In semiconductor memories represented by a DRAM having this arrangement, demands are recently arising for high-speed operation at low voltages. As the voltage decreases, a sense buffer (S/B) functioning as a read data bus amplifier employs a current detection type S/B capable of detecting and amplifying even a very small current difference with high detection sensitivity, instead of a conventional voltage detection type S/B for detecting and amplifying a voltage difference.
This current detection type S/B is constituted as shown in, e.g., FIG. 2. In FIG. 2, two read signal input terminals rgdbx and rgdbz are respectively connected to the two read data buses RLDBX and RLDBZ shown in FIG. 1C, and receive signals read out from a memory cell via a pair of bit lines BL and /BL.
Two p-channel transistors 21 and 22 have the drains connected to the read signal input terminals rgdbx and rgdbz, the sources connected to a high-potential power supply Vii, and the gates grounded. The p-channel transistors 21 and 22 are always ON and function as a constant current source for supplying a current I.
An amplifier activation signal input terminal sbez receives an amplifier activation signal which changes to "H" in a read and to "L" in a write. When this amplifier activation signal changes to "H" in a read to select the S/B, a current difference is generated between a current I-I.sub.D input from one p-channel transistor 21 to an amplifier 23 and a current I-I.sub.D ' input from the other p-channel transistor 22 to the amplifier 23 in accordance with a potential difference based on the amplitude of the pair of bit lines BL and /BL.
The amplifier 23 amplifies this current difference and outputs it from an output terminal rdbz via inverters 24 and 25. As shown in FIG. 2, this amplifier 23 is constituted by appropriately connecting p-channel transistors and n-channel transistors, and can be realized by a known arrangement. In this example, an amplified read detection signal is output in a single phase from one output terminal rdbz. But, another output terminal may be formed at the output of an inverter 26.
FIG. 3 is a circuit diagram for explaining the operation of the sense amplifier shown in FIG. 1C in more detail. In FIG. 3, the same reference numerals as in FIG. 1C denote the same parts. Two S/As 31 and 32 shown in FIG. 3 are sense amplifiers arranged above and below a given memory cell array 3, as shown in FIG. 1C.
An S/B 33 has the arrangement shown in FIG. 2, and is connected to the S/As 31 and 32 (n-channel transistors 8 for selecting the column line CL) via read data buses RGDBX, RGDBZ, RLDBX, and RLDBZ. A W/A 34 is a write amplifier for amplifying a signal in a data write, and is connected to the S/As 31 and 32 (n-channel transistors 9 for selecting the column line CL) via write data buses WGDBX, WGDBZ, WLDBX, and WLDBZ.
As an address (not shown) externally input to the DRAM, a row address and a column address are input time-divisionally from the same address terminal. The row address is decoded by a row decoder (word decoder) 35 and supplied as a block select signal for selecting one of the blocks shown in FIG. 1B.
This block select signal is supplied to the S/As 31 and 32 as a sense amplifier activation signal for activating the sense amplifier, and also supplied to a read controller 37 and a write controller 38 (to be described later). In FIG. 3, the block select signal (sense amplifier activation signal) activates one S/A 31, while keeping the other S/A 32 non-active.
The column address is decoded by a column decoder 36 and supplied to the n-channel transistors 8 and 9 in each of the S/As 31 and 32 to control the ON/OFF state. A sense amplifier at the intersection between a block selected by the block select signal and a column selected by the column select signal is selected to read out/write data from/in the corresponding memory cell.
The read controller 37 cascade-connects a p-channel transistor 39 and an n-channel transistor 40 to connect their gates, and has a CMOS structure in which the transistors 39 and 40 are respectively connected to the high-potential power supply Vii and ground. The gate common to the transistors 39 and 40 receives the above-described block select signal. The drain commonly connected to the transistors 39 and 40 outputs the read enable signal rclex.
When the block select signal supplied to the read controller 37 changes to "H" in a data read, the p-channel transistor 39 and n-channel transistor 40 in the read controller 37 are turned off and on, respectively. Then, the read enable signal rclex changes to "L". As indicated by the thick line in FIG. 3, the current detection type S/B 33 flows and amplifies a read detection current from the connected high-potential power supply Vii to the ground of the read controller 37.
In a standby state (precharge state), the block select signal changes to "L" to turn the p-channel transistor 39 on and the n-channel transistor 40 off. Thus, no read detection current flows.
The write controller 38 controls whether to write data in memory cells in a block selected by the block select signal on the basis of the block select signal and write status signal. The write status signal changes to "L" in a read and to "H" in a write. When the write status signal supplied to the write controller 38 changes to "H", the n-channel transistor 10 for selecting the write column line WCL is turned on. The n-channel transistor 9 of the S/A 31 selected by the block select signal and column select signal is turned on to write data via the write data buses WGDBX, WGDBZ, WLDBX, and WLDBZ using the S/A 31.
In the related art, the read controller 37 ON/OFF-controls the internal transistors 39 and 40 on the basis of the block select signal. But, this block select signal is supplied in both a data read and write. In a selected block, the read enable signal rclex changes to "L" not only in a read but also in a write. The read data buses RGDBX, RGDBZ, RLDBX, and RLDBZ are precharged to "H" in a standby state in which no amplifier is used.
As a result, a current undesirably flows from the S/B 33 to the read controller 37 via the read data buses RGDBX, RGDBZ, RLDBX, and RLDBZ regardless of a write, so current consumption in a write increases. An unwanted read detection current flowing in a write may influence the write detection current to cause a malfunction.
In FIG. 3, the read detection current flows from the high-potential power supply Vii of the S/B 33 to the ground potential of the read controller 37. To the contrary, the DRAM may be constituted to flow the read detection current from the high-potential power supply Vii of the read controller 37 to the ground potential of an S/B 33', as shown in FIG. 4.
In FIG. 4, the n-channel transistors 7 to 10 used in the S/As 31 and 32 of FIG. 3 are replaced by p-channel transistors 7' to 10'. In FIG. 4, the block select signal, write status signal, and S/B activation signal have polarities opposite to those in FIG. 3, and change to "L" in an active state and to "H" in a non-active state.
In FIGS. 3 and 4, the read data buses RLDBX and RLDBZ, and the read data buses RGDBX and RGDBZ are respectively reversed. The read enable signal rclex in FIG. 3 is replaced with a read enable signal rclez having the opposite polarity in FIG. 4. Note that "x" suffixed the signal name indicates a signal which changes to "L" in an active state, and "z" indicates a signal which changes to "H" in an active state.
In this arrangement, the S/B 33' is constituted as shown in FIG. 5. In FIG. 5, the same reference numerals with a symbol "'" as in FIG. 2 denote the same parts. In FIG. 5, n-channel transistors 21' and 22' and p- and n-channel transistors in an amplifier 23' are connected to the high-potential power supply Vii and ground potential, reversely to those in FIG. 2. Further, the S/B activation signal sbez is replaced with sbex.
Even in the arrangements in FIGS. 4 and 5, as indicated by the bold line in FIG. 4, a current undesirably flows from the read controller 37 to the S/B 33' via the read data buses RGDBX, RGDBZ, RLDBX, and RLDBZ regardless of a write, so current consumption in a write increases.